• Faculty of the Year Award 2012, Caribbean Students Organization

• Faculty of the Year Award 2005,2006,2007, 2009-2011 Department of Computer Science

• Faculty Member of the Year Award 2004, MSU Student Government

• Faculty Award 2003

• Faculty of the Year Award 2003, Caribbean Students Organization

• Faculty of the Year Award 2001,2002, Department of Computer Science

• Midwestern State University Hardin Professor 2000

• Who is Who in America

• Who’s Who in Science and Engineering

• International Who's Who of Professionals

• Member of UPE- Upsilon Pi Epsilon - Honor Society for the Computer Science

• Member of Bill Norris Shark Club (Control Data Corporation) 

• Best Control Data Corporation System Analyst Panam/Pacific Region 

• Best Control Data Corporation System Analyst Brazil 

• Control Data Corporation Professional Excellence

1. “Code Performance Measurement as an Educational Tool," (with K. Schoby and S. Carpenter), in the Proceedings of the 18th Annual CCSC South Central Conference, in the Journal of Computing in Small Colleges, April 2007, Wichita Falls, TX, pp. 184-190. 

2. "Communication Scheduling with Re-routing based on Static and Hybrid Techniques," (with D. Surma and E. H.-M. Sha) in the Journal on Circuits, Systems and Computers, October 2004, Volume 13, Number 5, pp. 1039-1064.

3. "Instruction Level Parallelism of Non-Uniform Acyclic Loops," (with P. Xue and H. Bui), in the Proceedings of the 15th Annual CCSC South Central Conference, in the Journal of Computing in Small Colleges, April 2004, Austin, TX, pp. 279-286. 

4. "On-Line Instructional Testing in a Mobile Environment," (with C. Wuthrich, G. Kalbfleisch, and T. Griffin), in the Proceedings of the Fourteenth Annual CCSC South Central Conference, in the Journal of Computing in Small Colleges, April 2003, Jackson, MS, pp. 23-29.

5. "Improving Cache Hit Ratio by Extended Referencing Cache Lines," (with C.-T. Wang), in the Proceedings of the Fourteenth Annual CCSC South Central Conference, in the Journal of Computing in Small Colleges, April 2003, Jackson, MS, pp. 118-123.

6. "Efficient Polynomial-Time Nested Loop Fusion with Full Parallelism," (with T. W. O'Neil and E. H.-M. Sha) in the International Journal of Computers and Their Applications, March 2003, vol. 10, n. 1, pp. 9-24. 

7. "An Experiment with Hardware Implementation of Edge Enhancement Filters," (with T. Griffin), in the Proceedings of the Thirteenth Annual CCSC South Central Conference, in the Journal of Computing in Small Colleges, April, 2002, Seguin, TX, pp. 24-31.

8. "The Real Problem of Virtual Reality or Designing Faster Computers," in the Faculty Papers of Midwestern State University, edited by Lansing Smith, Series 3, Vol. XIV, 2001, pp 171-183.

9. "Efficient Loop Scheduling and Pipelining for Applications with Non-uniform Loops," (with S. Tongsima, C. Chantrapornchai and E. H.-M. Sha) in the IASTED International Journal of Parallel and Distributed Systems and Networks, vol. 1, n. 4, pp. 204-211.

10. "Probabilistic Loop Scheduling for Applications with Uncertain Execution Time," (with S. Tongsima, C. Chantrapornchai, D. Surma and E. H.-M. Sha) in the IEEE Transactions on Computers, January 2000, vol. 49, n. 1, pp. 65-80. 

11. "Reducing Data Hazards on Multi-pipelined DSP Architecture with Loop Scheduling," (with S. Tongsima, C. Chantrapornchai and E. H.-M. Sha) in the Journal of VLSI Signal Processing, vol. 18, pp. 111-123. 

12. "A Brief Survey of Techniques of Loop Transformation," (with L. Plummer and R. Halverson), in the Proceedings of the Tenth Annual South Central Conference, in the Journal of Computing in Small Colleges, April 1999, Austin, TX, pp. 86-94. 

13. "Implementing a True Undergraduate Research Experiment," in the Proceedings of the Tenth Annual South Central Conference, in the Journal of Computing in Small Colleges, April 1999, Austin, TX, pp. 86-94. 

14. "Scheduling of Uniform Multi-Dimensional Systems under Resource Constraints," (with E. H.-M. Sha) in the IEEE Transactions on VLSI Systems, December 1998, vol. 6, n. 4, pp. 719-730. 

15. "An Efficient Implementation of Nested Loop Control Instructions for Fine Grain Parallelism",(with V. Andronache and R. Simpson) in the Proceedings of the Ninth Annual South Central Conference, in the Journal of Computing in Small Colleges, April 1998, Jackson, MS, pp. 67-76. 

16. "SILENCE: An Educational Tool for Teaching Instruction-Level Parallelism," (with L. Plummer, J. Hua, S. Brunet and R. Halverson) in the Proceedings of the Ninth Annual South Central Conference, in the Journal of Computing in Small Colleges, April 1998, Jackson, MS, pp. 185-192. 

17. "Minimization of Memory Access Overhead for Multi-Dimensional DSP Applications via Multi-Level Partitioning and Scheduling," (with E. H.-M. Sha and J. Q. Wang) in the IEEE Transactions on Circuits and Systems vol. II - Analog and Signal Processing, September 1997, vol. 44, n. 9, pp. 741-753.

18. "Communication Sensitive Loop Scheduling for DSP Applications," (with E. H.-M. Sha and S. Tongsima) in the IEEE Transactions on Signal Processing, May 1997, vol. 45, n. 5, pp. 1309-1322.  

19. "Multi-Dimensional Interleaving for Synchronous Circuit Design Optimization," (with E. H.-M. Sha and L.-F. Chao) in the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, February 1997, vol. 16, n. 2, pp. 146-159. 

20. "Decisions! Decisions! or Avoiding Computer Speculation," in the Faculty Papers of Midwestern State University, edited by Lansing Smith, Series 3, Vol. XIV, 2003, pp 77-86.      

21. "Optimal Data Scheduling for Uniform Multi-Dimensional Applications," (with E. H.-M. Sha and J. Q. Wang) in the IEEE Transactions on Computers, vol. 45, n. 12, December 1996, pp. 1439-1444.       

22. "Achieving Full Parallelism using Multi-Dimensional Retiming," (with E. H.-M. Sha) in the IEEE Transactions on Parallel and Distributed Systems, vol. 7, n. 11, November 1996, pp. 1150-1163.       

23. "Synchronous Circuit Optimization via Multi-Dimensional Retiming," (with E. H.-M. Sha) in the IEEE Transactions on Circuits and Systems vol. II - Analog and Signal Processing, vol. 43, n. 7, July 1996, pp. 507-519.       

24. "Optimizing DSP Flow Graphs via Schedule-Based Multi-Dimensional Retiming," (with E. H.-M. Sha and S. C. Bass) in the IEEE Transactions on Signal Processing, January 1996, pp. 150-155.   

   

1. “Accountability for Quality in Higher Education” (with Patti Hamilton) in the Proceedings of the 2011 International Conference on Frontiers in Education: Computer Science and Computer Engineering, Las Vegas, NV, July, 2011, pp162-166.

2. “Computer Cluster Scheduling through Genetic Algorithms” (with Ainsley Joseph), in the Proceedings of the 2009 International Conference on Parallel and Distributed Processing Techniques and Applications, Las Vegas, NV, July 2009, pp. 393-397.

3. "Scheduling Multi-Dimensional Loops in a Computer Cluster", (with K. P. Mayfield, A. Joseph, S. Black and H. Bui), in the Proceedings of the 19th International Conference on Computer Applications in Industry and Engineering, November, 2006, Las Vegas, NV, pp. 78-82. 

4. "Scheduling Multi-Dimensional Loops in a Computer Cluster", (with K. P. Mayfield, A. Joseph, S. Black and H. Bui), in the Proceedings of the 19th International Conference on Computer Applications in Industry and Engineering, November, 2006, Las Vegas, NV, pp. 78-82. 

5. ''Reducing Inter Iteration Dependency Delays in Multiprocessor Systems for Large Graphs'', (with M. Sheliga and E. Sha), in the Proceedings of the 3rd International Conference on Cybernetics and Information Technologies, Systems and Applications, CITSA 2006, July 2006 Orlando, Florida, paper I237GG (selected as the best paper in the session: Interdisciplinary Research, Analogy based Modeling and Problem Solving).

6. ''Computerized Analysis of Flowing Conditions for Use of Chemical Sticks in Natural Gas Wells'', (with J. Rhoads and R. Halverson), in the Proceedings of the 3rd International Conference on Cybernetics and Information Technologies, Systems and Applications, CITSA 2006, July 2006 Orlando, Florida, pp. 58-63.

7. "A Computerized Ecological Assessment of Families of Beetles from the Chihuahuan Desert of West Texas" (with M. Shipley), in the Proceedings of the 18th ISCA International Conference on Computer Applications in Industry and Engineering, November, 2005, Honolulu, Hawaii, pp. 21-25.

8. "Computational Model of Temperatures in a Covered Water Body Responding to Solar Insolation" (with J. Rhoads and J. Faulk), in the Proceedings of the 18th ISCA International Conference on Computer Applications in Industry and Engineering, November, 2005, Honolulu, Hawaii, pp. 15-20.

9. "Multi-Dimensional Retiming applied to Cluster Computing" (with K. P. Mayfield and H. H. Tsai), in the Proceedings of the 11th International Conference on Information System Analysis and Synthesis, July, 2005, Orlando, Florida, pp. 124-129.

10. "Network Centric Improvements to Resource Caching" (with R. Zuck, A. Williams, B. Kair, H. Bui, and C. Stringfellow), in the Proceedings of the IEEE Consumer Communications and Networking Conference, January, 2005, Las Vegas, Nevada (nominated for the best paper award). 

11. "Adjusting Web Caching Computers to Reduce Communication Channel Allocation" (with R. Zuck, A. Williams, B. Kair, H. Bui, and C. Stringfellow), in the Proceedings of the ISCA 17th International Conference on Computer Applications in Industry and Engineering, November, 2004, Orlando, Florida. 

12. "Message Hiding in Images," (with C. Crenshaw), in the Proceedings of the 16th International Conference on Computer Applications in Industry and Engineering, November, 2003, Las Vegas, NV, pp. 28-31. 

13. "A Brief Study of Cooperative Web Caching Protocols in Cellular Networks," (with A. K. Gelli, J. Nalluru, and E. Freeman), in the Proceedings of the 16th International Conference on Computer Applications in Industry and Engineering, November, 2003, Las Vegas, NV, pp. 36-39.

14. "Adaptive Virtual Web Caches," (with J. Nalluru, S. Movva, and A. Gelli), in the Proceedings of the IASTED International Conference on Communications, Internet and Information Technology (CIIT 2003), November, 2003, Scottsdale, AZ, pp. 209-213. 

15. "Modeling and Retiming Non-Uniform Acyclic Loops," (with P. Xue, H. Bui, and A. Joseph), in the Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems (PDCS 2003), November, 2003, Marina Del Rey, CA, pp. 328-332. 

16. "Instructional Testing through Wireless Handheld Devices," (with C. Wuthrich, R. Halverson, and T. Griffin), in the Proceedings of the Frontiers in Education Conference (FIE '03), November, 2003, Boulder, CO, pp. S4E-7 - S4E-12.

17. "Improving Cacheability and Responsiveness of an Interactive Wireless Web Application," (with A. Gelli, E. Freeman, and C. Wuthrich), in the Proceedings of the International Conference on Computer, Communication and Control Technologies (CCCT '03) July, 2003, Orlando, FL, pp. 158-163 (selected for best paper award). 

18. "Mobile Web Caching in a Hostile Environment," (with S. Movva, T. Griffin, and G. Kalbfleisch), in the Proceedings of the 17th AeroSense-Battlespace Digitization and Network-Centric Systems III, April, 2003, Orlando, FL, pp. 102-110. 

19. "Adjusting Web Cache Replacement Algorithms According to User Connectivity," (with S. Movva, A. Gelli, and G. Kalbfleisch), in the Proceedings of the International Signal Processing Conference, April 2003, Dallas, TX, paper number 269. 

20. "A Brief Study on Web Caching Applied to Mobile Web Applications," (with G. Kalbfleisch, W. Deckert and R. Halverson), in the Proceedings of the 18th International Conference on Computers and their Applications, 2003, Honolulu, HI, pp. 442-445.

21. "Predicting Conditional Branch Outcomes on a Sobel Edge Detecting Filter," (with Z. Jin), in the Proceedings of the International Conference on Acoustics, Sound and Signal Processing, Orlando, FL, May, 2002, vol. III, pp. 3192-3195.

22. "A Study on the FPGA Implementation of Edge Detection Algorithms," (with T. Griffin), in the Proceedings of the 14th International Conference on Computer Applications in Industry and Engineering, Las Vegas, NV, November, 2001. 

23. "Branch Prediction of Conditional Nested Loops Trough an Address Queue," (with Z. Jin and V. Andronache), in the Proceedings of the 14th International Conference on Parallel and Distributed Computing Systems, Dallas, TX, August, 2001, pp. 97-102. 

24. "Theoretical Constraints on Multi-Dimensional Retiming Design Techniques," (with R. J. Bailey, D. C. Defoe, R. H. Halverson, and R. P. Simpson), in the Proceedings of the AeroSense-Aerospace/Defense Sensing, Simulation and Controls, Orlando, FL, April, 2001, Vol. 4388, pp. 238-245. 

25. "Design and Analysis of Efficient Application-Specific On-Line Page Replacement Techniques for Distributed Memory Systems," (with V. Andronache and E. H.-M. Sha), in the Proceedings of the 12th IASTED International Conference on Parallel and Distributed Computing and Systems, Las Vegas, NV, November, 2000, pp. 551-556. 

26. "Improving Nested Loops' ILP on a Parallel ASIC Design," (with R. P. Light, W. Maxfield, B. Reed, and E. Sha), in the Proceedings of the 13th International Conference on Parallel and Distributed Computing Systems, Las Vegas, NV, 2000, pp. 105-110. 

27. "A Study of Software Pipelining for Multi-dimensional Problems," (with R. J. Bailey, D. C. Defoe, R. H. Halverson, and R. P. Simpson), in the Proceedings of the 13th International Conference on Parallel and Distributed Computing Systems, Las Vegas, NV, August, 2000, pp. 426-431. 

28. "Design and Analysis of Efficient Application-Specific On-line Page Replacement Techniques," (with E. Sha, and V. Andronache), in the Proceedings of the 10th Great Lakes Symposium on VLSI, Evanston, IL, March, 2000, pp. 123-128. 

29. "A VHDL Design Optimization for Two-Dimensional Filters," (with R. Light, J. Song, R. Halverson and R. P. Simpson), in the Proceedings of the IS&T/SPIE's 12th International Symposium on Electronic Imaging, San Jose, CA, January, 2000, vol. 3970, pp. 59-69. 

30. "True Undergraduate Research: Foundation for Graduate Studies and Critical Thinking," (with S. B. Carpenter), in the Proceedings of the 1999 Frontiers in Education Conference, November 1999, San Juan, Puerto Rico, session 13c5, pp. 7-12. 

31. "A Study on Multimedia over IP and Multicast Routing Protocols," (with D. Ruetsch, and S. B. Carpenter), in the Proceedings of the Third IASTED International Conference on Internet and Multimedia Systems and Applications, Nassau, Grand Bahamas, October, 1999, pp.378-382. 

32. "ASIC Design for Conditional Nested Loops with Predicate Registers," (with B. Sinclair, and R. Light), in the Proceedings of the 1999 Midwest Symposium on Circuits and Systems, Las Cruces, NM, August, 1999, pp. WA1.3. 

33. "Design of 2-D Filters using a Parallel Processor Architecture," (with R. Light, V. Andronache, and E. H.-M. Sha), in the Proceedings of the ISCA 12th International Conference on Parallel and Distributed Computing Systems, Fort Lauderdale, FL, August, 1999, pp. 528-533. 

34. "Fine Tuning the GALE Edge Detection Method," (with T. P. Donovan), in the Proceedings of the 1999 IEEE International Symposium on Circuits and Systems, Orlando, FL, May, 1999, paper 70.5. 

35. "A Genetic Algorithm Approach to Edge Detection on Image Processing Applications," (with T. P. Donovan), in the Proceedings of the 11th International Conference on Computer Applications in Industry and Engineering, Las Vegas, NV, November, 1998, pp. 71-74. 

36. "Performance Evaluation of Parallel Implementation of Nested Loop Control Structure," (with S. Brunet, V. Andronache, and R. Halverson), in the Proceedings of the 11th International Conference on Computer Applications in Industry and Engineering, Las Vegas, NV, November, 1998, pp. 215-218. 

37. "Z Specification for an Internet Movie Screening," (with C. E. Lieberman, A. E. Newsom, and S. B. Carpenter), in the Proceedings of the 11th International Conference on Computer Applications in Industry and Engineering, Las Vegas, NV, November, 1998, pp. 67-70.  

38. "Edge Detection through the Use of a Combined Genetic Algorithm-Linear Technique approach," (with T. P. Donovan), in the Proceedings of the 1998 Midwest Symposium on Circuits and Systems, Notre Dame, IN, August, 1998, pp. 310-313.

39. "An Efficient Implementation of Nested Loop Control Instructions for Super Scalar Processors," (with V. Andronache and R. P. Simpson), in the Proceedings of the 1998 Midwest Symposium on Circuits and Systems, Notre Dame, IN, August, 1998, pp. 82-85. 

40. "Nested Loops Optimization for Multiprocessor Architecture Design,"(with A. Leonardi and E. H.-M. Sha), in the Proceedings of the 1998 Midwest Symposium on Circuits and Systems, Notre Dame, IN, August, 1998, pp. 415-418. 

41. "A Perfect Branch Prediction Technique for Conditional Loops,"(with V. Andronache and R. Simpson), in the Proceedings of the World Multiconference on Systemics, Cybernetics and Informatics (SCI'98) and the 4th International Conference on Informatics Systems Analysis and Synthesis (ISAS'98), Orlando, FL, July, 1998, vol. 2, pp. 651-657. 

42. "Optimizing Circuits with Confidence Probability using Probabilistic Retiming,"(with E. H.-M. Sha, C. Chantrapornchai and S. Tongsima), in the Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, Monterey, CA, May, 1998, pp. WAA11-8. 

43. "Precise-MD: A Software Tool for Resources Constrained Scheduling of Multi-Dimensional Applications," (with J. Hua, O. Rashid, R. Halverson and R. Simpson), in the Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, Monterey, CA, May, 1998, pp. TAA15-4. 

44. "GALE: a Combined Genetic Algorithm-Linear Technique Approach to Edge Detection," (with T. Donovan), in the Proceedings of the SPIE Aerospace/Defense Sensing and Controls, Orlando, FL, April, 1998, vol. 3387, pp. 156-164. 

45. "An Object-Oriented Hardware/Software Co-Design Paradigm," (with O. Rashid and R. Halverson), in the Proceedings of the 13th International Conference on Computers and their Applications, Honolulu, Hawaii, March, 1998, pp. 440-443. 

46. "A Parallel Implementation of Robotic Path Planning with the Framed-Quadtree Data Structure," (with H. Guo and R. Szczerba), in the Proceedings of the 10th International Conference on Computer Applications in Industry and Engineering and Systems, San Antonio, TX, December, 1997, pp. 9-12. 

47. "Efficient Loop Scheduling and Pipelining for Applications with Non-uniform Loops," (with E. H.-M. Sha, C. Chantrapornchai and S. Tongsima), in the Proceedings of the 9th International Conference on Parallel and Distributed Computing and Systems, Washington, D.C., October, 1997, pp. 363-368.

48. "Probabilistic Rotation: Scheduling Graphs with Uncertain Execution Time" (with E. H.-M. Sha, C. Chantrapornchai and S. Tongsima), in the Proceedings of the International Conference on Parallel Processing 1997, Chicago, IL, August 1997, pp. 292-295.

49. "Scheduling with Confidence for Probabilistic Data Flow Graphs," (with E. H.-M. Sha, C. Chantrapornchai and S. Tongsima), in the Proceedings of the 1997 Great Lakes Symposium on VLSI, Urbana-Champaign, IL, March 1997, pp. 150-155.

50. "Software Engineering Requirements Analysis in the Classroom", in the Proceedings of the Eighth Annual South Central Conference, in the Journal of Computing in Small Colleges, vol. 12, n. 4, March 1997, pp. 48-57.

51. "Algorithm and Hardware Support for Branch Anticipation," (with E. H.-M. Sha, R. D. Ju and T. Z. Yu), in the Proceedings of the 1997 Great Lakes Symposium on VLSI, Urbana-Champaign, IL, March 1997, pp. 163-168.

52. "Synthesis of Multi-Dimensional Applications in VHDL,"(with E. H.-M. Sha) in the Proceedings of the 1996 International Conference on Computer Design, Austin, TX, October, 1996, pp. 530-535. 

53. "SHARP: Efficient Loop Scheduling with Data Hazard Reduction on Multiple Pipeline DSP Systems," (with E. H.-M. Sha, S. Tongsima, and C. Chantrapornchai) in the Proceedings of the 1996 IEEE Workshop on VLSI Signal Processing, VLSI Signal Processing, IX, editors: Wayne Burleson, Konstantinos Konstantinides, and Teresa Meng, San Francisco, CA, November 1996, pp. 253-262. 

54. "Polynomial-time Nested Loop Fusion with Full Parallelism,"(with E. H.-M. Sha and C. Lang) in the Proceedings of the 1996 International Conference on Parallel Processing, Bloomingdale, IL, August, 1996, vol. 3, pp. 9-16. 

55. "Fully Parallel Hardware/Software Codesign for Multi-Dimensional DSP Applications," (with E. H.-M. Sha and M. Sheliga) in the Proceedings of the 4th International Workshop on Hardware/ Software Co-design, Pittsburgh, PA, March 1996, pp. 18-25. 

56. "A Parameterized Index-Generator for the Multi-Dimensional Interleaving Optimization," (with E. H.-M. Sha) in the Proceedings of the 6th Great Lakes Symposium on VLSI, Ames, IA, March 1996, pp. 66-71. 

57. "Multi-Level Partitioning and Scheduling under Local Memory Constraint," (with E. H.-M. Sha and J. Q. Wang) in the Proceedings of the Seventh IEEE Symposium on Parallel and Distributed Processing, San Antonio, TX, October, 1995, pp. 612-619. 

58. "Push-up Scheduling: Optimal Polynomial-time Resource Constrained Scheduling for Multi-Dimensional Applications," (with E. H.-M. Sha) in the Proceedings of the IEEE/ACM International Conference on Computer Aided Design, San Jose, CA, November, 1995, pp. 588-591.   

59. "Multi-Dimensional Interleaving for Time-and-Memory Design Optimization," (with E. H.-M. Sha and L.-F. Chao) in the Proceedings of the IEEE International Conference on Computer Design, Austin, TX, October, 1995, pp. 440-445.     

60. "Memory Efficient Fully Parallel Nested Loop Pipelining," (with E. H.-M. Sha and L.-F. Chao) in the Proceedings of the 24th International Conference on Parallel Processing, Oconomowoc, WI, August, 1995, vol. II, pp. 182-185.

61. "Architecture-Dependent Loop Scheduling via Communication-Sensitive Re-mapping," (with E. H.-M. Sha and S. Tongsima) in the Proceedings of the 24th International Conference on Parallel Processing, Oconomowoc, WI, August, 1995, vol. II, pp. 97-104.  

62. "Memory/Time Optimization of 2-D Filters," (with E. H.-M. Sha) in the Proceedings of the 1995 IEEE International Conference on Acoustics, Speech & Signal Processing, Detroit, MI, May 1995, vol. 5, pp. 3223-3226.  

63. "Optimizing Synchronous Systems for Multi-Dimensional Applications," (with E. H.-M. Sha and L.-F. Chao) in the Proceedings of the 1995 IEEE European Design and Test Conference, Paris, France, March, 1995, pp. 54-58.   

64. "Communication Sensitive Rotation Scheduling," (with E. H.-M. Sha and S. Tongsima) in the Proceedings of the IEEE International Conference on Computer Design, Cambridge, MA, October, 1994, pp. 150-153.  

65. "Full Parallelism in Uniform Nested Loops using Multi-Dimensional Retiming," (with E. H.-M. Sha) in the Proceedings of the 23rd International Conference on Parallel Processing, Saint Charles, IL, August, 1994, vol. II, pp. 130-133.

66. "Loop Pipelining for Scheduling Multi-Dimensional Systems via Rotation," (with E. H.-M. Sha and S. C. Bass) in the Proceedings of the 31st Design Automation Conference, San Diego, CA, June, 1994, pp. 485-490 (nominated for the best paper award).

67. "Partitioning and Retiming of Multi-Dimensional Systems," (with E. H.-M. Sha and S. C. Bass) in the Proceedings of the IEEE International Symposium on Circuits and Systems, London, England, May, 1994, vol. 4, pp. 227-230.

68. "Schedule-Based Multi-Dimensional Retiming," (with E. H.-M. Sha and S. C. Bass) in the Proceedings of the 8th International Parallel Processing Symposium, Cancun, Mexico, April, 1994, pp. 195-199.

MSU PUBLICATIONS

1. "The Real Problem of Virtual Reality or Designing Faster Computers," in Faculty Papers, Midwestern State University, Series 3, Volume XV, 2000, pp. 77-86. 

2. "Decisions! Decisions! or Avoiding Computer Speculation," in Faculty Papers, Midwestern State University, Series 3, Volume XIV, 2001, pp. 171-183. 

3. “When Computer Security Fails,” MSU Faculty Forum, November, 2015, to be published in Faculty Papers, Midwestern State University.

BOOK REVIEWS:

  

1. "Pipelined and Parallel Computer Architectures," (by Saijan G. Shiva) book review in IEEE Concurrency, Vol. 6, no. 2, April 1998, pp. 92. 

2. "iWarp Anatomy of a Parallel Computing System," (by Thomas Gross and David R. Ohallaron) book review in IEEE Concurrency, vol. 7, n. 3, July 1999, pp. 92-93. 

3. The Essentials of Computer Organization and Architecture, Fourth Edition, by Null and Lobur (fifth edition to be published).

4. Computer Systems. Fourth Edition, 2016, by J. Stanley Warford, (reviewers mentioned in page xxx of preface of the fifth edition).

5. Computer Organization and Architecture, 9/e, 2016, by William Stallings. Publisher: Pearson. , (reviewers mentioned in page XXII of preface of the tenth edition).

6. Internet Security; How to Defend Against Attackers on the Web by Mike Harwood, 2019, publisher: Jones & Bartlett Learning

7. Essentials of Computer Organization and Architecture, by Linda Null and Julia Lobur, 5th edition. 2021.

TECHNICAL REPORTS, ETC.:

1. "Schedule-Based Multi-Dimensional Retiming on Data-Flow Graphs," (with E. H.-M. Sha and S. C. Bass) in Research Report CSE-TR-93-012b, Department of Computer Science and Engineering, University of Notre Dame. 

2. "Loop Pipelining for Scheduling Multi-Dimensional Systems via Rotation," (with E. H.-M. Sha and S. C. Bass) in Research Report CSE-TR-93-013, Department of Computer Science and Engineering, University of Notre Dame.

3. "Partitioning and Retiming of Multi-Dimensional Systems," (with E. H.-M. Sha and S. C. Bass) in Research Report CSE-TR-93-014, Department of Computer Science and Engineering, University of Notre Dame.

4. "Nested Loop Transformation for Full Parallelism," (with E. H.-M. Sha) in Research Report CSE-TR-94-011, Department of Computer Science and Engineering, University of Notre Dame.

5. "Communication Sensitive Rotation Scheduling," (with E. H.-M. Sha and S. Tongsima) in Research Report CSE-TR-94-015, Department of Computer Science and Engineering, University of Notre Dame.

6. "Architecture Dependent Loop Scheduling via Communication Sensitive Remapping," (with E. H.-M. Sha and S. Tongsima) in Research Report CSE-TR-94-024, Department of Computer Science and Engineering, University of Notre Dame.

7. "Multi-Dimensional Interleaving for Synchronous Circuit Design Optimization," (with E. H.-M. Sha and L.-F. Chao) in Research Report CSE-TR-94-035, Department of Computer Science and Engineering, University of Notre Dame.

8. "Carrot-Hole Data Scheduling and Adaptive Partitioning for Memory Traffic Minimization," (with E. H.-M. Sha and J. Q. Wang) in Research Report CSE-TR-95-10, Department of Computer Science and Engineering, University of Notre Dame.

9. "Multi-Level Partitioning and Scheduling under Local Memory Constraint," with E. H.-M. Sha and J. Q. Wang) in Research Report CSE-TR-95-11, Department of Computer Science and Engineering, University of Notre Dame.

10. "Reducing Pipeline Hazard via Rotation Scheduling," (with S. Tongsima, C. Chantrapornchai, E. H.-M. Sha and J. Q. Wang) in Research Report CSE-TR-95-20, Department of Computer Science and Engineering, University of Notre Dame.

11. "Loop Pipelining Algorithm for Non-Uniform Increasing Dependency Loops," (with S. Tongsima, and E. H.-M. Sha) in Research Report CSE-TR-96-07, Department of Computer Science and Engineering, University of Notre Dame.

12. "Branch Anticipation Using Loop Pipelining for Resource Constrained Systems," (with T. Z. Yu, and E. H.-M. Sha) in Research Report CSE-TR-96-11, Department of Computer Science and Engineering, University of Notre Dame.

13. "Probabilistic Retiming: A Circuit Optimization Technique," (with S. Tongsima, C. Chantrapornchai, and E. H.-M. Sha) in Research Report CSE-TR-96-15, Department of Computer Science and Engineering, University of Notre Dame.

14. "Probabilistic List Scheduling: an Algorithm for Producing Initial Schedules for Probabilistic Rotation Scheduling," (with S. Tongsima, C. Chantrapornchai, and E. H.-M. Sha) in Research Report CSE-TR-96-16, Department of Computer Science and Engineering, University of Notre Dame.

15. "Algorithms and Architecture Support for Pipelining and Scheduling Nested Loops with Conditions," (with T. Z. Yu, E. H.-M. Sha and D.-C. Ju) in Research Report CSE-TR-97-08, Department of Computer Science and Engineering, University of Notre Dame.

16. "Collision Graph based Communication Reduction Techniques for Parallel Systems," (with D. Surma and E. H.-M. Sha) in Research Report CSE-TR-97-14, Department of Computer Science and Engineering, University of Notre Dame.

17. "Efficient Polynomial-Time Nested Loop Fusion with Full Parallelism," (with T. W. O'Neil and E. H.-M. Sha) in Research Report CSE-TR-99-09, Department of Computer Science and Engineering, University of Notre Dame.

18. "Skill Training for Customer Satisfaction" in the Proceedings of the 8th Annual Quality Management and Applied Statistics Symposium, Minneapolis, MN, Oct., 1990, pp.63-70.

19. "O Metodo de Analise de Informacoes atraves de Relacoes Binarias" (The Method of Information Analysis through Binary Relations) in the Proceedings of the 18th Congresso Nacional de Informatica, Sao Paulo, Brazil, September 1985, pp.927-932.

20. "Disponibilidades Presentes e Futuras de Centros Computacionais para Simulacao Numerica," (Current and Future Availability of Computer Centers for Numerical Simulation) in the Proceedings of the I Seminario de Modelagem Numerica do Mar, Sao Jose dos Campos, Brazil, December, 1984, pp. 361-365.

21. "Status do Setor Operacional do Centro de Satelites Ambientais" (Current Status of the Operational Division of Environmental Satellites", in the Proceedings of the II Encontro de Usuarios de Produtos de Satelites Ambientais, Sao Jose dos Campos, Brazil, September, 1989, pp. 31-34.